岗位职责:Job descriptions:1. will work on following Mixed signal IP design: high frequency fractional-N PLL，digital DLL, digital LDO, analog LDO. OSC and high speed interface design.2. work closely with layout designer for layout implementation.3. silicon testing, characterization and debugging.

任职资格:Qualification:1. MSEE 4+ years experience in Mixed signal design.2. Experience in following IP related area: digital PLL/DLL, CDR (phase interpolator), digital LDO, High speed custom logic design and High speed driver/receiver, delta-sigma ADC/DAC, digital low pass filter3. Experience in mixed-signal processing using Matlab is a plus4. Experience in verilog/verilogA coding is a plus.5. Experience in 28n, or FinFet is a plus.6. Familiar with IP views (.LEF, .v, .Lib) is a must.7. Experience in ncverilog/vcs,Spice, Spectre AMS.