RESPONSIBILITIES:
· Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
· Perform verification on all DFT structures
· Generate DFT related timing constraints and work with PD team for timing closure
· Generate and verify DFT structural patterns and functional patterns
· Participate in ATE bring-up and debug the DFT patterns on ATE
· Design and implement other DFX (debug, characterization, yield etc) logics