澜起科技
设计验证工程师30万 - 45万 苏州 | 3年以上 | 硕士及以上 | 全职
职位福利:五险一金,年度旅游,技术领先,成长空间大,技能培训,节日礼物,十五薪,股票期权
发布时间:2020-11-25 发布者:Peter 投递简历
描述:
JOB DESCRIPTION:
- Participate ASIC digital verification for various IP/SoC projects;
- Create verification plans with designers;
- Develop DV architecture and verification environment;
- Verification execution and sign-off;
SKILLS MANDATORY:
- Excellent team working style;
- Solid IP/SoC verification background:
- Mass production for verified IP/SoC
- Master with 2> years working experiences on ASIC digital verification
- Production experiences on verification strategies and testplans;
- Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Production experiences on ARM buses, such as AXI/AMBA/APB is a plus;
- Familiar with verification tools ;
- Familiar with Linux, csh/Python or any script languages;
- Good English skills (read and write).