We are a team working on producing the highly optimized hardware IP for the ARC family of 32-bit configurable processors.  We are looking for an engineer like you to be part of the team to work on our world-class micro-processors that allow our customers develop highly optimized and very sophisticated embedded designs.
 
Responsibilities
- To define (micro)architecture specification and implement RTL design of microprocessors
- To optimize designs for performance, speed, size and power
- To work closely with verification team and contribute to verification strategy and help in debug fails
- To provide technical leadership to a team of CPU hardware design engineers
Requirements
- A minimum of 5-8 years of experience in ASIC design
- Deep knowledge and experience in RISC microprocessor architecture
- Hands-on experience in multi-core, cache coherency is a big plus
- Excellent grasp of RTL design (Verilog or VHDL)
- Good understanding of design for synthesis to achieve specified power, frequency, and area targets
- Familiar with EDA tools such as, VCS, VERDI, SPYGLASS, etc.
- Good knowledge of programming at assembly and C/C++ level
- Excellent communications skills in English
- Good demonstration of enthusiasm, drive and diligence
- Keen to work in a multi-site global development team