Work with global and local Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron APU chips including block level (full chip) floor planning, timing closure, place&route, physical verification. The flow build and maintain, new technology node research. 

任职要求：
1.Good communication skills, strong interpersonal skills and the flexibility
2.Dedicated, hardworking and good team player
3.Familiar with Back-End (physical design) EDA tools, ICCII, INVS, primetime, etc
4.Experiments in 16nm or lower porocess
5.Familiar with Unix/Linux environment and scripting
6.Good listening, writing and speaking English is a plus
 
BS, with 5 years or more experiments in physical design
MS, with 3 years or more experiments in physical design