Responsibilities:
1.Perform BE design from netlist to gds, including floorplan/placement/CTS/ROUTE/physical verification.
2.Perform Low Power design/power analysis/formal verification/STA-ECO flow.
3.Solve deep sub-micron design problems such as leakage, power, signal integrity, timing closure, DRC/DFM etc.
4.Work with EDA engineer and vendor to debug tool functionality and bugs.
5.Develop Perl/TCL/Shell scripts to enhance IC physical design flow and methodology.



Requirements:
1.Bachelor’s degree or above, major in Electronics Engineering.
2.Complete knowledge of full design IC implementation and signoff experience.
3.Good understanding and experience in 28nm/16nm/14nm/7nm etc. advanced technology.
4.Familiar with EDA tools, such as ICC2/INNOVUS/TEMPUS/CALIBRE/VOLTUS/REDHAWK.
5.Minimum 5 years of independent experience in top/block chip design.
6.Skill of written Perl/TCL/Shell scripts.
7.Self-driven and willing to work under pressure.
8.Good teamwork and strong responsibility.