岗位描述
1、熟悉半导体工艺流程、器件物理结构
  Familiar with semiconductor process flow, device physical structure
2、掌握calibre/ICV/PVS物理验证工具，并能够独立开发DRC/LVS
  Proficient at calibre/ICV/PVS physical verification tools, to develop DRC/LVS independently
3、掌握StarRC/QRC/xRC寄生参数抽取工具，并能够独立开发LPE
Proficient at StarRC/QRC/xRC parasitic parameter extract, to develop LPE independently
4、掌握Virtuoso版图设计工具，能够独立完成DRC/LVS/LPE的验证
Proficient at Virtuoso, complete DRC/LVS/LPE verification independently
5、学习TCL/perl等脚本语言，实现开发与验证自动化
To study TCL/perl script, realize Runset development and verification automatization 
6、客户PDK-Runset方面的设计支持
PDK application support at customer’s request
7、工程师的PDK知识培训
Engineer’s PDK knowledge training
8、其他：完成部门经理（上级主管）交办的其他任务。
Other: complete the tasks assigned by department manager.

所需教育水平与技能 (EDUCATION AND EXPERTISE REQUIRED)
1、电子工程，半导体物理，微电子等专业大学本科毕业以上。
Bachelor degree, or above, in EE，semiconductor physics, microelectronics etc.
2、具备较扎实的半导体物理、器件和相关的集成电路制造工艺知识，并熟悉代工厂的集成电路设计支持流程
Solid knowledge in semiconductor physics, device physics and IC processes, familiar with foundry’s IC design support flow. 
3、在集成电路设计公司或代工企业有3年以上独立从事DRC/LVS/版图设计/PDK集成等文件编写和验证方面的工作经验，或有相关经验的优秀应届本科毕业生/研究生；
Above 3 year working experiences with DRC/LVS/layout/PDK-integration in IC design house or foundry(BS/MS graduate well experienced in related IC design support package is also acceptable).
4、熟练使用EXPERT和CADENCE-LAYOUT等集成电路版图设计工具，熟练使用DRACULA/CALIBRE/PAS等相关工具。
Well experienced in EXPERT and CADENCE EDA layout tools and experienced in DRACULA/CALIBRE/PAS tools.
5、熟悉UNIX操作系统
Very familiar with UNIX
6、流利的英语说、写、读流利。
Proficient English in speaking, writing, listening.