岗位描述
1、基于PAS平台/skill语言独立开发PDK library，包括pcell,callback,CDF,symbol view等。
To develop PDK library based on PAS/skill language independently, including pcell,callback,CDF,symbol view.
2、熟练使用Cadence virtuoso，calibre等相关EDA工具，独立完成PDK的仿真验证及物理验证
Well experienced in Cadence virtuoso，calibre relevant EDA tools, complete physical verification and simulation verification independently.
3、熟悉器件物理结构、Layout Design Rule及spice model，能根据客户及工艺的具体要求完成PDK的开发
 Familiar with device physical structure, Layout Design Rule and spice model, to develop PDK based on customerand process requirement.
4、学习TCL/perl等脚本语言，实现PDK开发和验证的自动化
 To study TCL/perl script, realize PDK development and verification automatization 
5、客户PDK-Pcell方面的设计支持
PDK application support at customer’s request
6、工程师的PDK知识培训
Engineer’s PDK knowledge training
7、其他：完成部门经理（上级主管）交办的其他任务。
Other: complete the tasks assigned by department manager.

所需教育水平与技能 (EDUCATION AND EXPERTISE REQUIRED)
1、电子工程，半导体物理，微电子等专业大学本科毕业以上。
Bachelor degree, or above, in EE，semiconductor physics, microelectronics etc.
2、具备较扎实的半导体物理、器件和相关的集成电路制造工艺知识，并熟悉代工厂的集成电路设计支持流程
Solid knowledge in semiconductor physics, device physics and IC processes, familiar with foundry’s IC design support flow. 
3、在集成电路设计公司或代工企业有3年以上独立从事DRC/LVS/版图设计/PDK集成等文件编写和验证方面的工作经验，或有相关经验的优秀应届本科毕业生/研究生；
Above 3 year working experiences with DRC/LVS/layout/PDK-integration in IC design house or foundry(BS/MS graduate well experienced in related IC design support package is also acceptable).
4、熟练使用EXPERT和CADENCE-LAYOUT等集成电路版图设计工具，熟练使用DRACULA/CALIBRE/PAS等相关工具。
Well experienced in EXPERT and CADENCE EDA layout tools and experienced in DRACULA/CALIBRE/PAS tools.
5、熟悉UNIX操作系统
Very familiar with UNIX
6、流利的英语说、写、读流利。
Proficient English in speaking, writing, listening.