Job Responsibility:
-  Digital design of communication IC.
-  Work with architect engineers to develop design specification of IP features
-  RTL Implementation in Verilog HDL, CDC check, synthesis and timing analysis
-  Work closely with verification and validation engineers to fix issues

Job Requirements:
-  MS major in ME/EE/CS or related
-  Experience with front-end IP/SoC design
-  Skills in RTL Coding, synthesis, timing analysis and closure
-  Knowledge of AMBA AXI/AHB/APB Bus
-  Experience with USB/PCIe/SATA controller design is a plus
-  Knowledge of FPGA development is a plus
-  Strong script skill in Perl/Tcl is a plus
-  Good english document reading and writing skills
-  Good communication skill
-  Quick learning skill