RESPONSIBILITIES:
-      Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
-      Perform verification on all DFT structures
-      Generate DFT related timing constraints and work with PD team for timing closure
-      Generate and verify DFT structural patterns and functional patterns
-      Participate in ATE bring-up and debug the DFT patterns on ATE
-      Design and implement other DFX (debug, characterization, yield etc) logics
 
REQUIREMENTS:
-      Master degree in EE/CS with at least 5 years’ experience, or Bachelor degree with at least 8 years’ experience in IC or semiconductor industry
-      Minimum 3 years of experience in DFx-related areas
-      Hands on working experience on ASIC DFT design and verification, familiar with entire ASIC design flow
-      Strong analytical/problem solving skills and pronounced attention to details.
-      Must be a self-starter and able to independently drive tasks to completion.
-      Strong interpersonal and communication skills