•    Develop verification methodology for embedded FPGAs
•    Perform manufacturability, design rule checks, and timing sign-off for embedded FPGAs
•    开发嵌入式 FPGA 的验证方法
•    执行嵌入式 FPGA 的可制造性、设计规则检查和时序签核
•    Bachelor degree or master degree in Micro-electronics
•    Basic experience with ASIC design tools
•    Familiar with Python, Tcl
•    Experience with Synopsys Primetime or equivalent commercial tools
•    Experience with Mentor Modelsim or equivalent commercial tools
•    Experience with Mentor Calibre or equivalent commercial tools
•    Have tape-out experience is a plus
•    微电子学学士或硕士学位
•    ASIC 设计工具的基本经验
•    熟悉Python、Tcl
•    使用 Synopsys Primetime 或同等商业工具的经验
•    使用 Mentor Modelsim 或同等商业工具的经验
•    使用 Mentor Calibre 或同等商业工具的经验
•    有流片经验者优先