•    Develop custom cell for embedded FPGA layout
•    Develop logic synthesis scripts to optimize embedded FPGA RTL netlists
•    为嵌入式 FPGA 布局开发定制单元
•    开发逻辑综合脚本以优化嵌入式 FPGA RTL 网表

•    Master degree in Micro-electronics
•    Familiar with Cadence Virtuoso or equivalent tools
•    Familiar with Synopsys Design Compiler or equivalent tools
•    Experience in developing standard cells in advanced technology nodes
•    Have tape-out experience is a plus
•    微电子学硕士
•    熟悉Cadence Virtuoso 或同等工具
•    熟悉 Synopsys Design Compiler 或同等工具
•    在先进技术节点开发标准单元的经验
•    有流片经验者优先